The invention relates to a shift register for safely providing a configuration bit, particularly a bit from a series of configuration bits which are needed for configuring programmable logic circuits.
In the case of programmable logic circuits, such as in the case of FPGAs (Field Programmable Gate Arrays), particularly high demands are placed on the reliability of the configuration bits. FPGAs are fully programmable by the user (“in the field”) and can perform a great number of the logic functions desired by the user, depending on the programming or configuration. FPGAs normally contain configurable logic blocks whose electrical connections are defined by the externally applied configuration bits and thus form a complex logic chip overall.
In commercially available variants of FPGAs, the configuration bits are stored in locally or peripherally arranged SRAMs and continually need to be available as logic levels in order to maintain the appropriately programmed electrical connection which has been set up or interrupted in the FPGA, or the FPGA's functional variant. When turning on or at the start of an operating period for an FPGA, the configuration bits are loaded into the individual SRAM blocks and are then available there over the entire operating period. The fact that the configuration bits need to be individually readable and writable, since each configuration bit represents an electrical connection which has been set up or interrupted in the FPGA, means that the peripheral complexity is very high in the case of this solution. In addition, the logic operation of the FPGA can be defined only when turning on or in the case of a reset or in an offline mode by reloading the SRAMs, but not in the short term, e.g. within one clock cycle.
Since the logic operation of an FPGA is defined by all of the configuration bits, disturbed configuration bits cause the entire programmable chip to malfunction.
With progressing miniaturization, the memory cells are becoming more sensitive toward fault mechanisms. In particular, ionizing radiation can “reprogram” individual SRAM cells when recent submicron technology is used. Frequently, even the potting compound or other materials within the chip contain alpha radiation sources as impurities.
In the event of a malfunction as a result of incorrect configuration bits, a partial configuration update or configuration change then needs to be performed for the memory cells which have been combined to produce an actuatable block or cluster and include a faulty memory cell. Since each memory cell needs to be addressed and have information written to it, a change of configuration is very time-consuming and the FPGA is not operational during this time. During reprogramming, it is also necessary to prevent the logic blocks provided in the FPGA from being active and sometimes connections from being briefly set which, in the extreme case, may result in short circuits between individual outputs.
U.S. Pat. No. 6,011,740 describes an arrangement comprising three latches or memory cells for use as configuration memory in FPGAs, which arrangement allows said FPGAs to be reprogrammed. FIG. 1 shows a corresponding arrangement based on the prior art. Three memory cells or latches MC1, MC2, MC3 connected in series in the circuit are provided, with switches S1, S2, S3 which can be controlled by suitable signals P1, P2, P3 being provided between the latches MC1, MC2, MC3, and the third latch MC3 having an inverter I connected downstream of it. The input of the first latch is connected by means of a controllable switch S4, which is controlled by a control signal P4, to a bit line, for example, which delivers a configuration bit KE which is used for programming. At the output of the second latch MC2, the configuration bit KA is then output continuously to a programming node in an FPGA. A suitable switching sequence for the controllable switches S1, S2, S3, S4 writes different configuration bits to all three latches. In parallel with the continuous output of the configuration bits KA, it is possible to close the switch S4, open the switch S3 and apply a new configuration bit KE (which is different from KA) in order to write said configuration bit to the latch MC1. Opening the switch S4 again and closing the switch S1 “shifts” the memory content of the memory cell MC1 to the cell MC2 and thus changes the configuration bit KA at the output. It is possible to change to the original configuration state again by closing the switch S3, which shifts the memory content of the latch MC3 to the latch MC1, and closing the switch S1, in order to restore the original configuration state. The latches based on the prior art can, as FIG. 2 shows, be connected by two back-to-back connected inverters I1, I2 to form a latch MC, with the input E and the output A respectively being formed by connecting nodes between the inverters I1, I2. Such an embodiment of a latch delivers the inverted level of the input value at its output (as a result of which the annular arrangement in FIG. 1 presupposes the inverter).
Although the circuit arrangement shown in FIG. 1 based on the prior art allows reprogramming of a configuration bit KA which is routed to a programming node in an FPGA, it requires considerable wiring complexity, because each circuit arrangement as shown in FIG. 1 needs to be connected to a bit line for each programming node—or for each configuration bit—and needs to be equipped with the wiring for the controllable switches. In the case of large scale integration and miniaturization in the submicron range, fault mechanisms—such as ionizing radiation (alpha particles)—may additionally alter the latch contents and may thus cause the FPGA to malfunction. In addition, the arrangement of the latches M1, M2, M3 in the form of an annular shift register permits just one change of configuration or one change of configuration bit twice in succession.
It is therefore an object of the present invention to provide a shift register for safely providing configuration bits, and particularly a shift register cell, which requires little complexity in terms of circuitry and permits configuration changes during operation.